In a fabrication of semiconductor devices, methods frequently attempt to verify a manufacturability of an integrated circuit (IC) design using a designated color of polygons (e.g., metal routes). Such color indicates a decomposition of the polygon. For instance, in a self-aligned double patterning (SADP) process a color frequently indicates a mandrel or non-mandrel region. By way of example, mandrels are formed on a hardmask, spacers are formed on each side of each of the mandrels, and the mandrels are subsequently removed. Next, the spacers are used to prevent an etching of covered portions of the hardmask, resulting in mandrel recesses (e.g., portion of the hardmask previously covered by the mandrels) and non-mandrel recesses (e.g., portions of the hardmask previously between the mandrels). Finally, the mandrel and non-mandrel recesses are filled with a metal, resulting in mandrel and non-mandrel metal routes, respectively. As such, determining a color of some polygons, such as, for instance, off-grid structures, short arms of an odd jog route, and jogs may be difficult to determine, particularly during a routing step in IC designs utilizing SADP processes. Furthermore, use of such color indeterminable routes may cause color decomposition issues, resulting in unmanufacturable IC designs utilizing SADP process. As such, many traditional methods avoid using color indeterminable routes, thereby resulting in a lower density of features in IC designs and in resulting IC devices.
A need therefore exists for a methodology enabling a generating of color undeterminable polygons (e.g., off-grid routes) in IC designs and for an apparatus for performing the method, particularly in IC designs utilizing SADP processes.